Recording Head Technology Drive Test Development Intern

What You Will Do

• Being responsible to include the requirements from design team into the drive code test and plan the experiment to checkout and monitor the result, including data analysis with a small test sample size before releasing functional test scripts to production team to cover more activities and provide design feedback to design team.  
• Work with DVL test team members to support transducer design activities within the Teparuk factory focusing on reader design evaluations.  
• Be expected to work with all DVL teams such as Drive Development Electrical Engineering Integration (EI) and Mechanical Engineering Integration teams (MEI). Responsible for firmware support, including new test development, debugging and modification (Python) that will be used to support key technology and new design evaluations. 
• Manage test evaluation requests and provide the first level data analysis (JMP) including deep drive failure analysis.  
• Work collaboratively within a team environment of engineers to meet aggressive goals and high-quality standards. 
• Be assigned additional tasks and responsibilities that will positively contribute towards team, department, and company goals. 

Required Skills and Abilities

• Able to work under pressure and meet deadlines, while maintaining a positive attitude and providing exemplary customer service. 
• Open-minded and good attitude. 
• Good at programming, python is preferrable. 
• Fluent in English.

Your experience includes:

• Experience or background in recording physics is preferrable.  
• Scripting with JMP, Python is preferrable. 
• Good verbal and written communication. 
• Good presentation skills.

About our group: 
 
Drive Verification Line (DVL) Test Development is under Characterization & Analytic Group (CAG) for research and development manages drive-test setups and analyzes test results on overall new head designs to feedback the performance and reliability to the head design team for further development.  
 
Our mission is to provide physics-based understanding of reliability & Recording Sub-system (RSS) limiters, via new test development, expert execution, and advanced data analytics. We are responsible for designing, programming, debugging and modification of firmware applications to support all DVL tests, i.e., writer DVL (wDVL), reader DVL (rDVL) as well as mechanical DVL (mDVL).

About Us: 
 
With more than four decades of storage innovation, Seagate empowers humanity to thrive in the data age and helps people and businesses navigate the ever-expanding data landscape.  
 
We craft precision-engineered, cutting-edge solutions that help the world store and manage exponential data growth. 
 
Seagate is powered by our talented, passionate, and diverse workforce of 40,000 employees across the globe who embody our core values: integrity, innovation, and inclusion. Striving towards excellence every single day, we show up with these values for our customers, business partners, shareholders, and communities alike. 
 
Join us and get inspired to make a difference in the datasphere!